Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Appli... Shubu Mukherjee

Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications - Shubu Mukherjee, SiFive Modern SoC’s for ADAS and other mission critical applications employ heterogeneous architectures consisting of application processors, vision and communication DSPs, and AI accelerators; each with different ISAs, toolchains, and levels of functional safety and security. Semiconductor suppliers to these markets will greatly benefit from the simplicity of a single ISA capable of addressing the performance requirements of these varied processor blocks, whose openness facilitates achieving high levels of both functional safety and secure computing. In this presentation, SiFive will highlight the progress it has made towards delivering safety-capable RISC-V processors with all necessary features for future automotive applications. For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: