#1 Ben Eater’s 8 Bit Computer (SAP-1) in an FPGA: The Registers

This is the first video in a series of videos on implementing Ben Eater’s 8 Bit Computer in an FPGA. Ben Eater’s 8 Bit Computer is actually based on a computer called the SAP-1 from the book “Digital Computer Electronics“ by Paul Malvino and Jerald Brown. I wanted to do a series of videos that present a practical introduction to FPGAs and I thought it might be interesting to build Ben Eater’s 8-bit computer in an FPGA. This could be a practical example to learn about FPGAs and how CPUs work at the same time. In this first video, we will implement a generic register module in a hardware definition language called Verilog. We can use this generic register module to implement all of the registers in the SAP-1 computer including the A and B registers, the Output register, the Memory Address register, and the Instruction register. Once we have completed implementing the SAP-1/Ben Eater 8-bit computer architecture, we will expand this design with more memory, more C