DAC 2019 Demo - Register Generator for Design Register Memory Management

The increasing number of registers in complex designs becomes a challenge for modeling and verification. Any change in register definition should be automatically propagated to software and hardware engineers to reduce the costs and time involved. The Aldec Register Generator tool allows to create the RTL model for hardware designers, UVM model for verification engineers, C header for software designers and a memory map documentation for users. This presentation will show how to prepare a RTL register model